AS9C25256M2036L Datasheet, PDF (19/30 Pages) Alliance Semiconductor Corporation – 2.5V 256/128K X 36 Synchronous Dual-port SRAM with 3.3V or 2.5V interface

AS9C25256M2036L
AS9C25128M2036L
®
Collision timing waveform^[2]
CLK_A
R/W_A
[5]
t_CCO
t_CH[1]
t_CYC[1]
t_CL[1]
t_WS
t_WH
t_AS
[4]
t_AH
ADDRESS_{A[3] Am}
Aa
Am
Aa
Aa
Am
Aa
Am
Am
Am
Am
Aa
Don’t care
COL_A
t_SCOL t_RCOL
CLK_B
R/W_B
ADDRESS_B[3]
t_AS
t_AH
Am
Ab
t_WS
t_WH
[4]
Am
Ab
t_CH[1]
t_CYC[1]
t_CL[1]
Ab
Am
Ab
Am
Am
Am
Am
Ab
COL_B
t_SCOL t_RCOL
Notes:
1. Parameters t_CYC,t_CH and t_CL are different in Flow-through and Pipeline mode of operation and can be different for different ports (Refer AC Timing characteristics).
2. Chip Selected (CE0 = L and CE1 =H). True for both ports.
3. Address indicated is the Internal Address used and is dependent on the Address counter control inputs for that cycle.
4. “Am” refers to matched address. “Aa” and “Ab” refer to any other valid address.
5. During address collision the data validity is guaranteed only if t_CCO is greater than the minimum specified (Refer AC timing characteristics).
9/30/04, v.1.3
Alliance Semiconductor
P. 19 of 30