AS4C256M16D3B Datasheet, PDF (19/41 Pages) Alliance Semiconductor Corporation – 12BCN 96 ball FBGA PACKAGE

AS4C256M16D3B-12BCN
VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are illustrate in
figure VREF(DC) tolerance and VREF AC-Noise limits. It shows a valid reference voltage VREF(t) as a
function of time. (VREF stands for VREFCA and VREFDQ likewise).
VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to
meet the min/max requirement in Table of “Single-Ended AC and DC Input Levels for Command and
Address”. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than +/- 1% VDD.
voltage
V_DD
VREF(DC) tolerance and VREF AC-Noise limits
V_SS
time
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are
dependent on VREF.
"VREF" shall be understood as VREF(DC), as defined in figure above, VREF(DC) tolerance and VREF AC-
Noise limits.
This clarifies, that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid
high or low level and therefore the time to which setup and hold is measured. System timing and voltage
budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the
input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and volt-
age associated with VREF AC-noise. Timing and voltage effects due to AC-noise on VREF up to the speci-
fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
Confidential
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Rev.1.0 April 2016