256M-DDR2-AS4C16M16D2 Datasheet, PDF (16/66 Pages) Alliance Semiconductor Corporation – fully sunchronous operation

256M DDR2 -AS4C16M16D2
! Off-chip drive (OCD) impedance adjustment
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Figure 4. OCD impedance adjustment sequence
Before entering OCD impedance adjustment, all MR should be programmed and
ODT should be carefully controlled depending on system environment
Start
EMRS:OCD calibration mode exit
EMRS:Drive(1)
DQ &DQS HIGH;DQS# LOW
EMRS:Drive(0)
DQ &DQS LOW;DQS# HIGH
Test
ALL OK
ALL OK
Test
EMRS:OCD calibration mode exit
EMRS:OCD calibration mode exit
EMRS:Enter Adjust Mode
EMRS:Enter Adjust Mode
BL=4 code input to all DQs
Inc, Dec, or NOP
BL=4 code input to all DQs
Inc, Dec, or NOP
EMRS:OCD calibration mode exit
EMRS:OCD calibration mode exit
EMRS:OCD calibration mode exit
End
Confidential
- 16/66 -
Rev.1.0
May 2015