2GB-AUTO-AS4C256M8D3 Datasheet, PDF (14/82 Pages) Alliance Semiconductor Corporation – 8 internal banks for concurrent operation

 
2Gb Auto-AS4C256M8D3
  l Mode Register MR0
The mode-register MR0 stores data for controlling various operating modes of DDR3 SDRAM. It controls burst
length, read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which
include various vendor specific options to make DDR3 DRAM useful for various applications. The mode register is
written by asserting low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while controlling the states of address
pins according to the following figure.
Table 5. Mode Register Bitmap
BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0^*1 0
0
0^*1
PPD
WR
DLL TM CAS Latency RBT 0
BL Mode Register (0)
BA1 BA0 MRS mode
00
MR0
01
MR1
10
MR2
11
MR3
A7 Mode
0 Normal
1 Test
A3 Read Burst Type
0 Nibble Sequential
1
Interleave
A1 A0
BL
00
8 (Fixed)
0 1 BC4 or 8 (on the fly)
10
BC4 (Fixed)
11
Reserved
A11 A10 A9
000
001
010
011
100
101
110
111
WR (cycles)
Reserved
5^*2
6^*2
7^*2
8^*2
10^*2
12^*2
14^*2
A6 A5 A4
000
001
010
011
100
101
110
CAS Latency
Reserved
5
6
7
8
9
10
111
11
A12 DLL Control for Precharge PD
0
Slow exit (DLL off)
A8 DLL Reset
1
Fast exit (DLL on)
0
No
1
Yes
Note 1: Reserved for future use and must be set to 0 when programming the MR.
Note 2: WR (write recovery for autoprecharge) min in clock cycles is calculated by dividing tWR (ns) by tCK (ns) and
rounding up to the next integer WRmin [cycles] =Roundup (tWR / tCK). The value in the mode register must be
programmed to be equal or larger than WRmin. The programmed WR value is used with tRP to determine tDAL.
Confidential
-14/82-
Rev.1.0 June 2015