AS4C512M8D3L Datasheet, PDF (13/86 Pages) Alliance Semiconductor Corporation – AS4C512M8D3L - 78-ball FBGA PACKAGE

4Gb DDR3L - AS4C512M8D3L
Figure 7. tMOD timing
T0
T1
T2
CK#
CK
COMMAND
VALID
VALID
VALID
ADDRESS
VALID
VALID
VALID
CKE
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
MRS
VALID
NOP/DES
NOP/DES
NOP/DES
NOP/DES
NOP/DES
VALID
VALID
VALID
VALID
VALID
Tb1
VALID
VALID
Tb2
VALID
VALID
Settings
Old Settings
ODT
ODT
RTT_Nom ENABLED prior and/or after MRS command
VALID
VALID
ODTLoff + 1
RTT_Nom DISABLED prior and after MRS command
VALID
VALID
VALID
VALID
VALID
Updating Settings
t_MOD
VALID
VALID
VALID
VALID
New Settings
VALID
VALID
VALID
TIME BREAK
Don't Care
The mode register contents can be changed using the same command and timing requirements during normal
operation as long as the DRAM is in idle state, i.e., all banks are in the precharged state with tRP satisfied, all data
bursts are completed and CKE is high prior to writing into the mode register. The mode registers are divided into
various fields depending on the functionality and/or modes.
Confidential
13
Rev. 2.0
Aug. /2014