AS4C1M16S-CI Datasheet, PDF (13/54 Pages) Alliance Semiconductor Corporation – Programmable Mode registers

AS4C1M16S-C&I
8 Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", A11 = “V”, A10 = “V”, A0-A9 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The Mode
Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in
the Mode register to make SDRAM useful for a variety of different applications. The default values of
the Mode Register after power-up are undefined; therefore this command must be issued at the
power-up sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the
mode register. Two clock cycles are required to complete the write in the mode register (refer to the
following figure). The contents of the mode register can be changed using the same command and
the clock cycle requirements during operation as long as both banks are in the idle state.
Table 5. Mode Register Bitmap
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 RFU* WBL Test Mode
CAS# Latency
BT
Burst Length
A9 Write Burst Mode
0
Burst
1
Single Bit
A8 A7 Test Mode
00
Normal
1 0 Vendor Use Only
0 1 Vendor Use Only
A3 Burst Type
0 Sequential
1 Interleave
A6 A5 A4 CAS# Latency
A2 A1 A0
Burst Length
00 0
Reserved
0
0
0
1
00 1
Reserved
0
0
1
2
01 0
2 clocks
0
1
0
4
01 1
3 clocks
0
1
1
8
10 0
Reserved
1
1
1 Full Page (Sequential)
All other Reserved
All other Reserved
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
CLK
T0
T1 T2 T3 T4 T5 T6
T7
T8
T9
T10
CKE
tMRD
CS#
RAS#
CAS#
WE#
A11
A10
A0-A9
Address Key
DQM
DQ
Hi-Z
tRP
PrechargeAll
Mode Register
Set Command
Any
Command
Figure 15. Mode Register Set Cycle
Don’t Care
Confidential
12
Rev. 2.0
March /2015