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| AS7C33256PFS32A Datasheet, PDF (12/20 Pages) Alliance Semiconductor Corporation – 3.3V 256K x 32/36 pipelined burst synchronous SRAM | |||
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®
Key to switching waveforms
Rising input
Falling input
donât care
Timing waveform of read cycle
CLK
tADSPS
ADSP
tADSPH
tCYC
tCH
tCL
ADSC
tADSCS
tADSCH
tAS
tAH
Address
A1
A2
LOAD NEW ADDRESS
A3
GWE, BWE
tWS
tWH
tCSS
CE0, CE2
tCSH
AS7C33256PFS32A
AS7C33256PFS36A
Undefined
CE1
ADV
OE
Dout
tADVS
tADVH
ADV inserts wait states
tOE
tLZOE
Q(A1)
tHZOEtOH
Q(A2)
tCD
Q(A2Ã01)
Q(A2Ã10)
tHZC
Q(A2Ã11) Q(A3) Q(A3Ã01) Q(A3Ã10)
Read
Q(A1)
Suspend
Read
Q(A1)
Read Burst Burst Suspend Burst Read Burst
Burst
Burst
Q(A2) Read Read
Read
Read Q(A3) Read
Read
Read DSEL
Q(A 2Ã01) Q(A 2Ã10) Q(A 2Ã10) Q(A 2Ã11)
Q(A 3Ã01) Q(A 3Ã10) Q(A 3Ã11)
Note: Ã = XOR when LBO = high/no connect; Ã = ADD when LBO = low. BW[a:d] is donât care.
11/30/04, v.3.1
Alliance Semiconductor
P. 12 of 20
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