AS4C128M16D3A-12BAN Datasheet, PDF (11/83 Pages) Alliance Semiconductor Corporation – Fully synchronous operation

AS4C128M16D3A-12BAN
z Reset Procedure at Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET
needs to be maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time
10ns).
2. Follow Power-up Initialization Sequence step 2 to 11.
3. The Reset sequence is now completed. DDR3 SDRAM is ready for normal operation.
Figure 5. Reset Procedure at Power Stable Condition
Ta
Tb
Tc
Td
Te
Tf
Tg
Th
Ti
CK#
CK
VDD
VDDQ
T=100ns
t_CKSRX
T=500µs
RESET#
CKE
COMMAND
Tmin=10ns
t_IS
t_IS
t_XPR
t_MRD
t_MRD
t_MRD
t_DLLK
t_MOD
Note 1
MRS
MRS
MRS
MRS
ZQCL
Tj
t_ZQinit
Note 1
Tk
VALID
BA
ODT
RTT
MR2
MR3
MR1
MR0
t_IS
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
VALID
t_IS
VALID
NOTE 1. From time point Td until Tk NOP or DES commands must be applied between MRS and ZQCL commands.
TIME BREAK
Don't Care
Confidential
-1183-
Rev. 1.0 May 2016