ASM5P2309A Datasheet, PDF (1/20 Pages) Alliance Semiconductor Corporation – 3.3V Zero Delay Buffer

September 2005
ASM5P2309A
ASM5P2305A
rev 1.6
3.3V Zero Delay Buffer
General Features
ƒ 15MHz to 133MHz operating range, compatible
with CPU and PCI bus frequencies.
ƒ Zero input - output propagation delay.
ƒ Multiple low-skew outputs.
ƒ Output-output skew less than 250pS.
ƒ Device-device skew less than 700pS.
ƒ One input drives 9 outputs, grouped as
4 + 4 + 1(ASM5P2309A).
ƒ One input drives 5 outputs (ASM5P2305A).
ƒ Less than 200 pS cycle-to-cycle jitter is compatible
with Pentium^® based systems.
ƒ Test Mode to bypass PLL (ASM5P2309A only,
Refer Select Input Decoding Table).
ƒ Available in 16pin 150-mil SOIC, 4.4 mm TSSOP
(ASM5P2309A), and in 8pin 150-mil SOIC
package (ASM5P2305A).
ƒ 3.3V operation, advanced 0.35µ CMOS
technology.
Functional Description
ASM5P2309A is a versatile, 3.3V zero-delay buffer
designed to distribute high-speed clocks. It accepts one
reference input and drives out nine low-skew clocks. It is
available in a 16-pin package. The ASM5P2305A is the
eight-pin version of the ASM5P2309A. It accepts one
reference input and drives out five low-skew clocks.
The -1H version of the ASM5P23XXA operates at up to
133MHz frequencies, and has higher drive than the -1
devices. All parts have on-chip PLLs that lock to an input
clock on the REF pin. The PLL feedback is on-chip and is
obtained from the CLKOUT pad.
The ASM5P2309A has two banks of four outputs each,
which can be controlled by the Select inputs as shown in
the Select Input Decoding Table. The select input also
allows the input clock to be directly applied to the outputs
for chip and system testing purposes.
Multiple ASM5P2309A and ASM5P2305A devices can
accept the same input clock and distribute it. In this case
the skew between the outputs of the two devices is
guaranteed to be less than 700pS.
All outputs have less than 200pS of cycle-to-cycle jitter.
The input and output propagation delay is guaranteed to be
less than 350pS, and the output to output skew is
guaranteed to be less than 250pS.
The ASM5P2309A and the ASM5P2305A are available in
two different configurations, as shown in the ordering
information table. The ASM5P2305A-1/ ASM5P2309A-1 is
the base part. The ASM5P2305A-1H/ ASM5P2309A-1H is
the high drive version of the -1 and its rise and fall times
are much faster than -1 part.
Block Diagram
PLL
REF
ASM5P2305A
CLKOUT
REF
CLK1
CLK2
CLK3
CLK4
PLL
MUX
S2
Select Input
Decoding
S1
ASM5P2309A
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA • Tel: [phone] • Fax: [phone] • www.alsc.com
Notice: The information in this document is subject to change without notice.