ASM5I9774A Datasheet, PDF (1/12 Pages) Alliance Semiconductor Corporation – 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer

June 2005
rev 0.3
ASM5I9774A
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
ƒ Output frequency range: 8.3MHz to 125MHz
ƒ Input frequency range: 4.2MHz to 62.5MHz
ƒ 2.5V or 3.3V operation
ƒ Split 2.5V/3.3V outputs
ƒ 14 Clock outputs: Drive up to 28 clock lines
ƒ 1 Feedback clock output
ƒ 2 LVCMOS reference clock inputs
ƒ 150 pS max output-output skew
ƒ PLL bypass mode
ƒ ‘SpreadTrak’
ƒ Output enable/disable
ƒ Pin compatible with MPC9774 and CY29774AI.
ƒ Industrial temperature range: –40°C to +85°C
ƒ 52Pin 1.0mm TQFP package
ƒ RoHS Compliance
Functional Description
The ASM5I9774A is a low-voltage high-performance
125MHz PLL-based zero delay buffer designed for high-
speed clock distribution applications.
The ASM5I9774A features two reference clock inputs and
provides 14 outputs partitioned in 3 banks of 5, 5, and 4
outputs. Bank A and Bank B divide the VCO output by 4 or
8 while Bank C divides by 8 or 12 per SEL(A:C) settings,
see Functional Table. These dividers allow output to input
ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each
LVCMOS compatible output can drive 50Ω series or
parallel terminated transmission lines. For series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:28.
The PLL is ensured stable given that the VCO is configured
to run between 200 MHz to 500 MHz. This allows a wide
range of output frequencies from 8.3 MHz to 125 MHz. For
normal operation, the external feedback input, FB_IN, is
connected to the feedback output, FB_OUT. The internal
VCO is running at multiples of the input reference clock set
by the feedback divider, see Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
Block Diagram
VCO_SEL
PLL_EN
TCLK_SEL
TCLK0
TCLK1
FB_IN
SELA
SELB
SELC
CLK_STP#
FB_SEL(1.0)
MR#/OE
+2
PLL
200-
+4
500MHZ
+2/+4
CLK
STOP
+2/+4
CLK
STOP
+4/+6
CLK
STOP
+4/+6/+8/+12
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QB4
QC0
QC1
QC2
QC3
FB_OUT
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: [phone] • Fax: [phone] • www.alsc.com
Notice: The information in this document is subject to change without notice.