ASM3P2508SP Datasheet, PDF (1/7 Pages) Alliance Semiconductor Corporation – Clock Synthesizer and Frequency Generator with Peak EMI reduction

February 2005
ASM3P2508SP
rev 0.4
Clock Synthesizer and Frequency Generator with Peak EMI reduction
Features
ƒ Dual PLL based Architecture
ƒ Operates with a 3.3V ±0.3V supply.
ƒ Generates an EMI optimized Spread Spectrum
PCI Clock output
ƒ Generates a high accuracy non Spread T1 clock of
±25ppm accuracy.
ƒ Generates a non spread system reference clock
ƒ Low power CMOS design.
ƒ Input frequency: 25 MHz.
ƒ Outputs:
Sys_ REF_CLK: 20 MHz
T1 Clock: 25 MHz (±25 ppm)
PCI_CLK: 33.33MHz Spread Spectrum
ƒ Frequency deviation: -0.5% (Typ).
ƒ Available in 8L SOIC Package.
Product Description
The ASM3P2508SP is a versatile Dual PLL based Clock
Synthesizer and Frequency Generator optimised and
designed specifically for three clock frequencies. The
PCI_CLK output from ASM3P2508SP reduces
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of all clock
dependent signals. ASM3P2508SP allows significant
system cost savings by reducing the number of circuit
board layers, ferrite beads & shielding that are
traditionally required to pass EMI regulations.
Block Diagram
PWRDNB
The ASM3P2508SP uses the most efficient and
optimized modulation profile approved by the FCC.
ASM3P2508SP modulates the output of a PLL in order to
“spread” the bandwidth of a synthesized clock, and more
importantly, decreases the peak amplitudes of its
harmonics. This results in a significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’ (SSCG).
In addition to the SSCG output, ASM3P2508SP
generates two high accuracy clock signals -
T1 Clock @ 25.00MHz with +/- 25ppm stability, and a
20MHz Sys_ REF_CLK.
Applications
The ASM3P2508SP is targeted towards Consumer,
Industrial, Data and Telecommunications applications.
Key Specifications
Description
Supply voltages
Input Frequency
Cycle-to-Cycle Jitter
Output Duty Cycle
Output Rise and Fall Time
SSC Modulation Rate
SSC Frequency Deviation
Specification
V_DD = 3.3V ±0.3V
25 MHz
175 pS ( Max)
45/55%
1.1 nS (Max)
30KHz (Typ)
-0.5% (Typ)
V_DD
T1_CLK
XIN/CLKIN
Osc
XOUT
Input
Divider
PLL 1
PLL 2
Modulation
Output
Divider
Output
Divider
Sys_REF_CLK
PCI_CLK
V_SS
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: [phone] • Fax: [phone] • www.alsc.com
Notice: The information in this document is subject to change without notice.