ASM2P3805AH Datasheet, PDF (1/13 Pages) Alliance Semiconductor Corporation – 3.3V CMOS Buffer Clock Driver

June 2005
ASM2P3805AH
rev 0.2
3.3V CMOS Buffer Clock Driver
Features
ƒ Advanced CMOS Technology
ƒ Guaranteed low skew < 500pS (max.)
ƒ Very low duty cycle distortion < 1.0nS (max)
ƒ Very low CMOS power levels
ƒ TTL compatible inputs and outputs
ƒ Inputs can be driven from 3.3V or 5V components
ƒ Two independent output banks with 3-state control
ƒ 1:5 fanout per bank
ƒ "Heartbeat" monitor output
ƒ V_CC = 3.3V ± 0.3V
ƒ Available in SSOP, SOIC and QSOP Packages
Functional Description
The ASM2P3805AH is a 3.3V, non-inverting clock driver
built using advanced CMOS technology. The device
consists of two banks of drivers, each with a 1:5 fanout and
its own output enable control. The device has a "heartbeat"
monitor for diagnostics and PLL driving. The MON output is
identical to all other outputs and complies with the output
specifications in this document. The ASM2P3805AH offers
low capacitance inputs.
The ASM2P3805AH is designed for high speed clock
distribution where signal quality and skew are critical. The
ASM2P3805AH also allows single point-to-point
transmission line driving in applications such as address
distribution, where one signal must be distributed to
multiple receivers with low skew and high signal quality.
Block Diagram
OE_A
IN_A
IN_B
OE_B
Pin Diagram
5
OA₁ – OA₅
5
OB₁ – OB₅
MON
V_CCA
OA₁
OA₂
OA₃
GND_A
OA₄
OA₅
GND_Q
OE_A
IN_A
1
20
2
19
A
3
S
18
4
M
17
2
5
3
16
6
8
15
0
7
5
14
A
8
H
13
9
12
10
11
V_CCB
OB₁
OB₂
OB₃
GND_B
OB₄
OB₅
MON
OE_B
IN_B
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: [phone] • Fax: [phone] • www.alsc.com
Notice: The information in this document is subject to change without notice.