ASM2I9942P Datasheet, PDF (1/10 Pages) Alliance Semiconductor Corporation – Low Voltage 1:18 Clock Distribution Chip

May 2005
ASM2I9942P
rev 0.3
Low Voltage 1:18 Clock Distribution Chip
Features
ƒ LVPECL Clock Input
ƒ 2.5V LVCMOS Outputs for Pentium II^TM*
Microprocessor Support
ƒ 200pS Maximum Targeted Output–to–Output
Skew
ƒ Maximum Output Frequency of 250MHz @3.3 V_CC
ƒ 32–Lead LQFP and TQFP Packaging
ƒ Single 3.3V or 2.5V Supply
ƒ Pin and Function compatible with MPC942P
Functional Description
The ASM2I9942P is a 1:18 low voltage clock distribution
chip with 2.5V or 3.3V LVCMOS output capabilities. The
device is offered in two versions; the ASM2I9942C has an
LVCMOS input clock while the ASM2I9942P has a
LVPECL input clock. The 18 outputs are 2.5V or 3.3V
LVCMOS compatible and feature the drive strength to drive
50Ω series or parallel terminated transmission lines. With
output-to-output skews of 200pS, the ASM2I9942P is ideal
as a clock distribution chip for the most demanding of
synchronous systems. The 2.5V outputs also make the
device ideal for supplying clocks for a high performance
Pentium II^TM microprocessor based design.
* Pentium II is a trademark of Intel Corporation
With low output impedance (≈12Ω), in both the HIGH and
LOW logic states, the output buffers of the ASM2I9942P
are ideal for driving series terminated transmission lines.
With an output impedance of 12Ω, the ASM2I9942P can
drive two series terminated transmission lines from each
output. This capability gives the ASM2I9942P an effective
fanout of 1:36. The ASM2I9942P provides enough copies
of low skew clocks for most high performance synchronous
systems.
The differential LVPECL inputs of the ASM2I9942P allow
the device to interface directly with a LVPECL fanout buffer
to build very wide clock fanout trees or to couple to a high
frequency clock source. The OE pins will place the outputs
into a high impedance state. The OE pin has an internal
pullup resistor.
The ASM2I9942P is a single supply device. The V_CC power
pins require either 2.5V or 3.3V. The 32 lead LQFP and
TQFP package is chosen to optimize performance, board
space and cost of the device. The 32–lead LQFP and
TQFP have a 7x7mm² body size with conservative 0.8mm
pin spacing.
Block Diagram
PECL_CLK
PECL_CLK
OE
(Int. Pullup)
Q0
Q1-Q16
Q17
Table 1. Function Table
OE
Output
0
HIGH IMPEDANCE
1
OUTPUTS ENABLED
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: [phone] • Fax: [phone] • www.alsc.com
Notice: The information in this document is subject to change without notice.