AS9C25512M2018L Datasheet, PDF (1/30 Pages) Alliance Semiconductor Corporation – 2.5V 512/256K x 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface

September 2004
Preliminary Information
AS9C25512M2018L
AS9C25256M2018L
®
2.5V 512/256K X 18 Synchronous Dual-port SRAM with 3.3V or 2.5V interface
Features
• True Dual-Port memory cells that allow simulta-
neous access of the same memory location
• Organisation: 524,288/262,144 × 18^[1]
• Fully Synchronous, independent operation on
both ports
• Selectable Pipeline or Flow-Through output
mode
• Fast clock speeds in Pipeline output mode: 250
MHz operation (9Gbps bandwidth)
• Fast clock to data access: 2.8ns for Pipeline out-
put mode
• Asynchronous output enable control
• Fast OE access times: 2.8ns
• Double Cycle Deselect (DCD) for Pipeline Out-
put Mode
• 19/18^[1]-bit counter with Increment, Hold and
Repeat features on each port
Note:
1. AS9C25512M2018L/AS9C25256M2018L
• Dual Chip enables on both ports for easy
depth expansion
• Interrupt and Collision Detection Features
• 2.5 V power supply for the core
• LVTTL compatible, selectable 3.3V or
2.5V power supply for I/Os, addresses,
clock and control signals on each port
• Snooze modes for each port for standby
operation
• 15mA typical standby current in power
down mode
• Available in 256-pin Ball Grid Array
(BGA), 144-pin Thin Quad Flatpack
(TQFP) and 208-pin fine pitch Ball Grid
Array (fpBGA)
• Supports JTAG features compliant with
IEEE 1149.1
Selection guide
Feature
-250
-200
-166
-133
Units
Minimum cycle time
4
5
6
7.5
ns
Maximum Pipeline clock frequency
250
200
166
133
MHz
Maximum Pipeline clock access time
2.8
3.4
3.6
4.2
ns
Maximum flow-through clock frequency
150
133
100
83
MHz
Maximum flow-through clock access time
6.5
7.5
10
12
ns
Maximum operating current
TBD
350
300
260
mA
Maximum snooze mode current
18
18
18
18
mA
9/24/04; v.1.2
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