AS8C803625 Datasheet, PDF (1/22 Pages) Alliance Semiconductor Corporation – Power down controlled by ZZ input

256K X 36, 512K X 18
3.3V Synchronous SRAMs
3.3V I/O, Burst Counter
Flow-Through Outputs, Single Cycle Deselect
AS8C803625
AS8C801825
Features
 256K x 36, 512K x 18 memory
configuration
 Supports fast access times:
- 7.5ns up to 117MHz clock frequency
 LBO input selects interleaved or linear
burst mode
 Self-timed write cycle with global write
control (GW), byte write enable (BWE),
and byte writes (BWx)
 3.3V core power supply
 Power down controlled by ZZ input
 3.3V I/O supply (VDDQ)
 Packaged in a JEDEC Standard 100-pin
thin plastic quad flatpack (TQFP)
Description
The 803625/801825 are high-speed SRAMs organized
as 256K x 36/512K x 18. The 803625/801825 SRAMs
contain write, data, address and control registers.
There are no registers in the data output path (flow-
through architecture). Internal logic allows the SRAM
to generate a self-timed write based upon a decision
which can be left until the end of the write cycle.
The burst mode feature offers the highest level of
performance to the system designer, as the
803625/801825 can provide four cycles of data for a
single address presented to the SRAM. An internal
burst address counter accepts the first cycle address
from the processor, initiating the access sequence. The
first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the
rising clock edge of the same cycle. If burst mode
operation is selected (ADV=LOW), the subsequent
three cycles of output data will be available to the user
on the next three rising clock edges. The orders of
these three addresses are defined by the internal burst
counter and the LBO input pin.
The 803625/801825 SRAMs utilize Alliance’s latest
high-performance CMOS process and are packaged in a
JEDEC standard 14mm x 20mm 100-pin thin plastic
quad flatpack (TQFP).
Pin Description Summary
A0 – A18
Address Inputs
CE
Chip Enable
CS0, CS1
Chip Selects
OE
Output Enable
GW
Global Write Enable
BWE
BW1, BW2, BW3, BW4⁽¹⁾
Byte Write Enable
Individual Byte Write Selects
CLK
Clock
ADV
Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO
Linear / Interleaved Burst Order
ZZ
Sleep Mode
I/O0 – I/O31, I/OP1 – I/OP4 Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
NOTE:
1. BW3 and BW4 are not applicable for 803625/801825.
5309 tbl 01
NOVEMBER 2010