AS8C803601 Datasheet, PDF(1/21 Page) Alliance Semiconductor Corporation – Three chip enables for simple depth expansion

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AS8C803601 Datasheet, PDF (1/21 Pages) Alliance Semiconductor Corporation – Three chip enables for simple depth expansion

256K x 36, 512K x 18

3.3V Synchronous ZBTâ¢ SRAMs

ZBTâ¢ Feature

3.3V I/O, Burst Counter

Pipelined Outputs

AS8C803601

AS8C801801

Features

Address and control signals are applied to the SRAM during one clock

â 256K x 36, 512K x 18 memory configurations

cycle, and two cycles later the associated data cycle occurs, be it read or write.

â Supports high performance system speed - 150MHz

The AS8C803601/801801 contain data I/O, address and control signal

(3.8ns Clock-to-Data Access)

registers. Output enable is the only asynchronous signal and can be

â ZBTTM Feature - No dead cycles between write and read cycles

â Internally synchronized output buffer enable eliminates the

used to disable the outputsat any given time.

A Clock Enable(CEN) pin allows operation of the toAS8C803601/ 801801

need to control OE

â Single R/W (READ/WRITE) control pin

â Positive clock-edge triggered address, data, and control

be suspended as long as necessary. All synchronous inputs are ignored when

(CEN)is high and the internal device registers will hold their previous values.

There are three chip enable pins (CE1, CE2,CE2) that allow the user

signal registers for fully pipelined applications

to deselect the device when desired. If anyone of these three are not asserted

â 4-word burst capability (interleaved or linear)

when ADV/LD is low, no new memoryoperation can be initiated. However,

â Individual byte write (BW1 - BW4) control (May tie active)

any pending data transfers (reads or writes) will be completed. The data bus

â Three chip enables for simple depth expansion

will tri-state two cycles after chip is deselected or a write is initiated.

â 3.3V power supply (Â±5%)

TheAS8C803601/801801 have an on-chip burst counter. In the burst

â 3.3V I/O Supply (V DDQ)

mode,the AS8C803601/801801 can provide fourcycles of data for a single

â Power down controlled by ZZ input

address presented to the SRAM. The order of the burst sequence is

â Packaged in a JEDEC standard 100-pin plastic thin quad

defined by the LBO input pin. The LBO pin selects between linear and

flatpack (TQFP).

interleaved burst sequence. The ADV/LD signal is used to load a new

external address (ADVL/ D =LOW) or increment the internal burst counter

Description

(ADV/LD = HIGH).

The AS8C803601/801801 SRAM utilize IDT's latest high-performance

The AS8C803601/801801 are3.3V high-speed 9,437,184 bit CMOS process, andare packaged ina JEDEC Standard 14mm x 20mm 100-

(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus pin thin plastic quad flatpack (TQFP) .

cycles when turning the bus around between reads and writes, or writes and

reads. Thus, they have been given the name ZBTMT, or Zero Bus Turnaround.

Pin Description Summary

A0-A18

CE1, CE2, CE2

R/W

Address Inputs

Chip Enables

Output E nable

Read/Write S ignal

CEN

Clock Enable

BW1, BW2, BW3, BW4

Individual Byte Write Selects

CLK

ADV/LD

Clock

Advance burst address / Load new address

LBO

Linear / In terleaved B urst Order

Sleep Mode

I/O0-I/O31, I/OP1-I/OP4

Data Input / O utput

VDD, VDDQ

Core P ower, I/ O Power

VSS

Ground

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

Static

Asynchronous

Synchronous

Static

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SEPTEMBER 2010

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