English
Language : 

AS8C803600 Datasheet, PDF (1/18 Pages) Alliance Semiconductor Corporation – Power down controlled by ZZ input
256K X 36, 512K X 18
3.3V Synchronous SRAMs
3.3V I/O, Burst Counter
Pipelined Outputs, Single Cycle Deselect
AS8C803600
AS8C801800
Features
◆ 256K x 36, 512K x 18 memory configurations
◆ Supports high system speed:
– 150MHz 3.8ns clock access time
◆ LBO input selects interleaved or linear burst mode
◆ Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
◆ 3.3V core power supply
◆ Power down controlled by ZZ input
◆ 3.3V I/O supply (VDDQ)
◆ Packaged in a JEDEC Standard 100-pin thin plastic quad
flatpack (TQFP)
Description
The AS8C803600/801800 are high-speed SRAMs organized as
Pin Description Summary
A0-A18
Address Inputs
CE
Chip Enable
CS0, CS1
Chip Selects
OE
Output Enable
GW
Global Write Enable
BWE
Byte Write Enable
BW1, BW2, BW3, BW4(1)
Individual Byte Write Selects
CLK
Clock
ADV
Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO
Linear / Interleaved Burst Order
ZZ
Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS
Ground
NOTE:
1. BW3 and BW4 are not applicable for other devices
256K x 36 / 512K x 18. The SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left
until the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the AS8C803600/801800 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The AS8C803600/801800 SRAMs utilize the latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-
pin thin plastic quad flatpack (TQFP),
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
5310 tbl 01
September 2010
1
.