AS8C403625 Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – Power down controlled by ZZ input

128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
AS8C403625
AS8C401825


Features
◆ _{128K x 36, 256K x 18 memory configurations}
◆ _{Supports fast access times:}
Commercial:
– 7.5ns up to 117MHz clock frequency
◆ _{LBO input selects interleaved or linear burst mode}
◆ _{Self-timed write cycle with global write control (GW), byte write}
enable (BWE), and byte writes (BWx)
◆ _{3.3V core power supply}
◆ _{Power down controlled by ZZ input}
◆ _{3.3V I/O}
◆ _{Optional - Boundary Scan JTAG Interface (IEEE 1149.1}
compliant)
◆ _{Packaged in a JEDEC Standard 100-pin plastic thin quad}
flatpack (TQFP),
Description
TheAS8C403625/1825 are high-speed SRAMs organized as
128K x 36/256K x 18. The AS8C403625/1825 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAM to gen-
erate a self-timed write based upon a decision which can be left until the
end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the AS8C403625/1825 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the LBO input pin.
The AS8C403625/1825 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP)
Pin Description Summary
A0-A17
Address Inputs
CE
CS0, CS1
Chip Enable
Chip Selects
OE
Output Enable
GW
Global Write Enable
BWE
Byte Write Enable
BW1, BW2, BW3, BW4⁽¹⁾
Individual Byte Write Selects
CLK
Clock
ADV
Burst Address Advance
ADSC
Address Status (Cache Controller)
ADSP
Address Status (Processor)
LBO
Linear / Interleaved Burst Order
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock
TDO
Test Data Output
TRST
JTAG Reset (Optional)
ZZ
Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
VDD, VDDQ
Core Power, I/O Power
VSS
Ground
NOTE:
1. BW3 and BW4 are not applicable for the AS8C401825.
1
.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Asynchronous
Synchronous
N/A
N/A
5280 tbl 01
SEPTEMBER 2010
DSC-5280/08