AS8C403600 Datasheet, PDF (1/17 Pages) Alliance Semiconductor Corporation – Power down controlled by ZZ input

128K x 36, 256K x 18
3.3V Synchronous SRAMs
3.3V I/O, Pipelined Outputs
Burst Counter, Single Cycle Deselect
AS8C403600
AS8C401800
Features
◆ _{128K x 36, 256K x 18 memory configurations}
◆ _{Supports high system speed:}
Commercial:
– 150MHz 3.8ns clock access time
◆ _{LBO input selects interleaved or linear burst mode}
◆ _{Self-timed write cycle with global write control ( Gl (W), byte}
write enable (BWE), and byte writes (BWx)
◆ _{3.3V core power supply}
◆ _{Power down controlled by ZZ input}
◆ _{3.3V I/O}
◆ _{Optional - Boundary Scan JTAG Interface (IEEE 1149.1}
compliant)
◆ _{Packaged in a JEDEC Standard 100-pin plastic thin quad}
flatpack (TQFP).
Pin Description Summary
A0-A17
Address In puts
CE
CS0, CS1
Chip Enab le
Chip Se lects
OE
Output E nable
GW
Global Write Enable
BWE
Byte Write Enable
BW1, BW2, BW3, BW4⁽¹⁾
Individual By te Write Se lects
CLK
Clock
ADV
Burst Ad dress Advance
ADSC
Address Status (Cache Controller)
ADSP
Address S tatus (Processor)
LBO
Linear / Interleaved B urst Order
TMS
Test Mode Select
TDI
Test Data Input
TCK
Test Clock
TDO
Test Data Output
ZZ
Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input / Ou tput
VDD, VDDQ
Core P ower, I/O P ower
VSS
Ground
NOTE:
1. BW3 and BW4 are not applicable for the AS8C401800.
Description
TheAS8C403600/1800 are high- speed SRAMs organized as
128K x 36/256K x 18. The AS8C403600/401800 SRAMs contain write,
data, address and control registers. Internal logic allows the SRAM to
generate a self-timed write based upon a decision which can be left until
the end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer,as theAS8C403600/1800 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (A( DV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the LBO input pin.
The AS8C403600/1800 SRAMs utilize the latest high- performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP).
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Synchronous
Synchronous
N/A
Synchronous
Asynchronous
Synchronous
N/A
N/A

September 2010
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