AS80SSTVF16857 Datasheet, PDF (1/12 Pages) Alliance Semiconductor Corporation – DDR 14-Bit Registered Buffer

July 2003
Advance Information
PulseC re AS80SSTVF16857
Š
DDR 14-Bit Registered Buffer
Features
Recommended Applications
• Differential clock signals
• Meets SSTL_2 class II specifications on outputs
• Supports SSTL_2 Class I and II specifications
• Low voltage operation – V_DD = 2.3V to 2.7V
• Available in 48-pin TSSOP and TVSOP package
• Operates at 2.3V to 2.7V for PC1600, PC2100, and
PC2700; 2.5V to 2.7V for PC3200
• Pinout and Functionality Compatible with JEDEC
Standard SSTV16857
• DDR memory modules
• Provides complete DDR DIMM logic solution
with PCV857
• SSTL_2-compatible data registers
Block Diagram
CLK ³⁸
CLKB ³⁹
RESETB ³⁴
D1
VREF
48
35
R
CLK
D1
To 13 other channels
Pin Configuration
Q1 1
48 D1
Q2 2
47 D2
GND 3
46 GND
VDDQ 4
45 VDD
Q3 5
44 D3
Q1
Q4 6
43 D4
Q5 7
42 D5
GND 8
41 D6
VDDQ ⁹
40 _D7
Q6 10
39 CLKB
Q7 11
38 CLK
VDDQ 12
37 VDD
GND 13
36 GND
Q8 14
35 VREF
Q9 ¹⁵
34 _RESETB
VDDQ ¹⁶
33 _D8
GND ¹⁷
32 _D9
Q10 ¹⁸
31 _D10
Q11 19
30 D11
Q12 20
29 D12
VDDQ 21
28 VDD
GND 22
27 GND
Q13 23
26 D13
Q14 24
25 D14
48-Pin TSSOP & TVSOP
6.10 mm body, 0.50 mm pitch = TSSOP
4.40 mm body, 0.40 mm pitch = TSSOP (TVSOP)
8/1/03; V.0.10
Alliance Semiconductor
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