AS7C4098A_06 Datasheet, PDF (1/11 Pages) Alliance Semiconductor Corporation – 5.0 V 256 K × 16 CMOS SRAM

February 2006
®
5.0 V 256 K × 16 CMOS SRAM
AS7C4098A
Features
• Pin compatible with AS7C4098
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6 ns output enable access time
• Low power consumption: ACTIVE
- 990mW/max @ 10 ns
• Low power consumption: STANDBY
- 55mW/max CMOS
• Individual byte read/write controls
Logic block diagram
A0
A1
A2
A3
A4
A6
A7
A8
A12
A13
I/O1–I/O8
I/O9–I/O16
WE
I/O
buffer
1024 × 256 × 16
Array
(4,194,304)
Control circuit
Column decoder
V_CC
GND
UB
OE
LB
CE
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangement for SOJ and TSOP 2
44-pin (400 mil) SOJ
TSOP2
A0 1
44
A1 2
43
A2 3
42
A3 4
41
A4 5
40
CE 6
39
I/O1
7
38
I/O2
8
37
I/O3
9
36
I/O4
10 ₃₅
V_CC 11 34
GND 12 33
I/O5
I/O6
13 ₃₂
14 31
I/O7
15 30
I/O8
16 29
WE 17 28
A5 18 27
A6 19 26
A7 20 25
A8 21 ₂₄
A9 22 23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
GND
V_CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
–10
–12
–15
–20
Unit
10
12
15
20
ns
5
6
6
6
ns
180
160
140
120
mA
10
10
10
10
mA
2/21/06, v 1.2
Alliance Semiconductor
P. 1 of 11
Copyright © Alliance Semiconductor. All rights reserved.