AS7C4098A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 2.5V 512K x 32/36 flowthrough burst synchronous SRAM

December 2004
AS7C25512FT32A
AS7C25512FT36A
®
2.5V 512K × 32/36 flowthrough burst synchronous SRAM
Features
• Organization: 524,288 words × 32 or 36 bits
• Fast clock to data access: 7.5/8.5/10.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 2.5V core power supply
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[18:0]
GWE
BWE
BW_d
BW_c
BW_b
BW_a
CE0
CE1
CE2
ZZ
OE
Selection guide
19
Power
down
LBO
CLK
CE
CLR
Q0
Burst logic
Q1
D
Q ¹⁹
17
CE
Address
register
CLK
D _DQd Q
Byte write
registers
CLK
D _DQc Q
Byte write
registers
CLK
D _DQb Q
Byte write
registers
CLK
D _DQa Q
Byte write
registers
CLK
D
Q
Enable
CE register
CLK
D _Enable Q
delay
register
CLK
512K × 32/36
19
Memory
array
36/32
36/32
4
OE
Output
buffer
Input
registers
CLK
36/32
DQ[a:d]
-75
-85
-10
Minimum cycle time
8.5
10
12
Maximum clock access time
7.5
8.5
10
Maximum operating current
275
250
230
Maximum standby current
90
80
80
Maximum CMOS standby current (DC)
60
60
60
Units
ns
ns
mA
mA
mA
12/23/04, v. 1.2
Alliance Semiconductor
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