AS7C4096A Datasheet, PDF (1/10 Pages) Alliance Semiconductor Corporation – 5.0V 512K x 8 CMOS SRAM

May 2005
Preliminary
AS7C4096A
®
5.0V 512K × 8 CMOS SRAM
Features
• Pin compatible to AS7C4096
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6 ns output enable access time
• Low power consumption: ACTIVE
- 880mW/max @ 10 ns
• Low power consumption: STANDBY
- 55mW/max CMOS
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
V_CC
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Input buffer
524,288 × 8
Array
(4,194,304)
Column decoder
Control
Circuit
I/O1
I/O8
WE
OE
CE
Pin arrangements
36-pin SOJ (400 mil)
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V_CC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 24
14 23
15 22
16 21
17 20
18 19
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
V_CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
44-pin TSOP 2
NC _{1 44}
NC _{2 43}
A0 3 42
A1 4 41
A2 5 40
A3 6 39
A4 7 38
CE 8 37
I/O1 9 36
I/O2 10 35
V_{CC 11 34}
GND 12 33
I/O3 13 32
I/O4 14 31
WE 15 30
A5 16 29
A6 17 28
A7 18 27
A8 19 26
A9 20 25
NC 21 24
NC 22 23
NC
NC
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
V_CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
NC
NC
Selection guide
Maximum address access time
Maximum outputenable access time
Maximum operating current
Maximum CMOS standby current
–10
–12
–15
10
12
15
5
6
6
160
140
120
10
10
10
–20
Unit
20
ns
6
ns
100
mA
10
mA
5/27/05, v. 1.1
Alliance Semiconductor
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