AS7C4096 Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 5V/3.3V 512K X8 CMOS SRAM

January 2005
AS7C4096
AS7C34096
®
5V/3.3V 512K × 8 CMOS SRAM
Features
• AS7C4096 (5V version)
• AS7C34096 (3.3V version)
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 1375 mW (AS7C4096) / max @ 12 ns
- 576 mW (AS7C34096) / max @ 10 ns
• Low power consumption: STANDBY
- 110 mW (AS7C4096) / max CMOS
- 72 mW (AS7C34096) / max CMOS
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 100 mA
Logic block diagram
Pin arrangements
V_CC
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Input buffer
I/O1
524,288 × 8
Array
(4,194,304)
I/O8
Column decoder
Control
Circuit
WE
OE
CE
36-pin SOJ (400 mil)
44-pin TSOP 2
A0 1 36
A1 2 35
A2 3 34
A3 4 33
A4 5 32
CE 6 31
I/O1 7 30
I/O2 8 29
V_CC 9
28
GND 10 27
I/O3 11 26
I/O4 12 25
WE 13 24
A5 14 23
A6 15 22
A7 16 21
A8 17 20
A9 18 19
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
V_CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
NC _{1 44}
NC _{2 43}
A0 3 42
A1 4 41
A2 5 40
A3 6 39
A4 7 38
CE 8 37
I/O1 9 36
I/O2 10 35
V_{CC 11 34}
GND 12 33
I/O3 13 32
I/O4 14 31
WE 15 30
A5 16 29
A6 17 28
A7 18 27
A8 19 26
A9 20 25
NC 21 24
NC 22 23
NC
NC
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
V_CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
NC
NC
Selection guide
–10
–12
–15
Maximum address access time
10
12
15
Maximum outputenable access time
5
6
7
Maximum operating current
AS7C4096
–
250
220
AS7C34096
160
130
110
AS7C4096
–
20
20
Maximum CMOS standby current
AS7C34096
20
20
20
–20
Unit
20
ns
8
ns
180
mA
100
mA
20
mA
20
mA
1/13/05; v.1.9
Alliance Semiconductor
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