AS7C3513C Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 3.3 V 32K X 16 CMOS SRAM

September 2006
Advance Information
AS7C3513C
®
3.3 V 32K X 16 CMOS SRAM
Features
• Industrial (-40^o to 85^oC) temperature
• Organization: 32,768 words × 16 bits
• Center power and ground pins for low noise
• High speed
- 10 ns address access time
- 5 ns output enable access time
• Low power consumption via chip deselect
• Upper and Lower byte pin
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
Logic block diagram
A0
A1
A2
A3
A4
A5
A6
A7
I/O0–I/O7
I/O8–I/O15
I/O
buffer
WE
V_CC
32,768 × 16
GND
Array
Control circuit
Address decoder
UB
OE
LB
CE
Pin arrangement
44-Pin SOJ (400 mil), TSOP 2
NC
1
A3
2
A2
3
A1
4
A0
5
CE
6
I/O0
7
I/O1
8
I/O2
9
I/O3
10
V_CC
11
GND
12
I/O4
13
I/O5
14
I/O6
15
I/O7
16
WE
17
A14
18
A13
19
A12
20
A11
21
NC
22
44
A4
43
A5
42
A6
41
OE
40
UB
39
LB
38
I/O15
37
I/O14
36
I/O13
35
I/O12
34
GND
33
V_CC
32
I/O11
31
I/O10
30
I/O9
29
I/O8
28
NC
27
A7
26
A8
25
A9
24
A10
23
NC
9/5/06, v 1.0
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