AS7C3513B Datasheet, PDF (1/10 Pages) Alliance Semiconductor Corporation – 3.3V 32K x 16 CMOS SRAM

March 2004
AS7C3513B
®
3.3V 32K×16 CMOS SRAM
Features
• Industrial and commercial temperature
• Organization: 32,768 words × 16 bits
• Center power and ground pins
• High speed
• 10/12/15/20 ns address access time
• 5, 6, 7, 8 ns output enable access time
• Low power consumption: ACTIVE
• 288 mW / max @ 10 ns
• Low power consumption: STANDBY
• 18 mW / max CMOS
• 6T 0.18m CMOS Technology
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• 44-pin JEDEC standard package
• 400 mil SOJ
• 400 mil TSOP 2
• ESD protection > 2000 volts
• Latch-up current > 200 mA
Logic block diagram
A0
A1
V_CC
A2
32K × 16
GND
A3
Array
A4
A5
A6
A7
I/O0–I/O7
I/O8–I/O15
I/O
buffer
Control circuit
WE
Column decoder
UB
OE
LB
CE
Pin arrangement
44-Pin SOJ, TSOP 2 (400 mil)
NC
1
A3
2
A2
3
A1
4
A0
5
CE
6
I/O0
7
I/O1
8
I/O2
9
I/O3
10
V_CC
11
GND
12
I/O4
13
I/O5
14
I/O6
15
I/O7
16
WE
17
A14
18
A13
19
A12
20
A11
21
NC
22
44
A4
43
A5
42
A6
41
OE
40
UB
39
LB
38
I/O15
37
I/O14
36
I/O13
35
I/O12
34
GND
33
V_CC
32
I/O11
31
I/O10
30
I/O9
29
I/O8
28
NC
27
A7
26
A8
25
A9
24
A10
23
NC
Selection guide
Maximum address access time
Maximum output enable access time
Maximum operating current
Maximum CMOS standby current
-10
-12
-15
-20
Unit
10
12
15
20
ns
5
6
7
8
ns
80
75
70
65
mA
5
5
5
5
mA
3/24/04, v.1.2
Alliance Semiconductor
P. 1 of 10
Copyright © Alliance Semiconductor. All rights reserved.