AS7C34098A-8TIN Datasheet, PDF (1/14 Pages) Alliance Semiconductor Corporation – fully static operation

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Rev. 1.4
AS7C34098A-8TIN
256K X 16 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Description
Initial Issue
“CE# ≧V_CC - 0.2V” revised as ”CE# ≦0.2V” for TEST CONDITION
of Average Operating Power supply Current
Icc1 on page3
Revised V_IH(max)/V_IL(min) in
DC ELECTRICAL CHARACTERISTICS
Added in t_BA/t_BHZ*/t_BLZ*
in AC ELECTRICAL CHARACTERISTICS
Added WRITE CYCLE 3 in TIMING WAVEFORMS
1.Revise “TEST CONDITION” for V_OH, V_OL on page 5
I_OH = -8mA revised as -4mA
I_OL =4mA revised as 8mA
2. Revise V_IH(max) & V_IL(min) note on page 5
V_IH(max) = V_CC + 2.0V for pulse width less than 6ns.
V_IL(min) = V_SS - 2.0V for pulse width less than 6ns.
Revised the address pin sequence of TSOP-II pin configuration on
page 3 in order to be compatible with industry convention. (No
function specifications and applications have been changed and all
the characteristics are kept all the same as Rev 1.3 )
Added t_BW in AC ELECTRICAL CHARACTERISTICS
Revised WRITE CYCLE 1,2 in TIMING WAVEFORMS
Issue Date
Jul.12.2012
Jul.19.2012
May.7.2013
Jun.04.2013
Sep.23.2013
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