AS7C34096A Datasheet, PDF (1/9 Pages) Alliance Semiconductor Corporation – 3.3V 512K x 8 CMOS SRAM

August 2004
AS7C34096A
®
3.3V 512K × 8 CMOS SRAM
Features
• Pin compatible to AS7C34096
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Low power consumption: ACTIVE
- 650 mW / max @ 10 ns
• Low power consumption: STANDBY
- 28.8 mW / max CMOS
Logic block diagram
V_CC
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Input buffer
524,288 × 8
Array
(4,194,304)
Column decoder
Control
Circuit
• Equal access and cycle times
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Pin arrangements
I/O1
36-pin SOJ (400 mil)
A0
A1
A2
A3
A4
CE
I/O1
I/O2
GVN^CD^C
I/O3
I/O4
WE
A5
A6
A7
A8
A9
1 36
2 35
3 34
4 33
5 32
6 31
7 30
8 29
9 28
10 27
11 26
12 25
13 24
14 23
15 22
16 21
17 20
18 19
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
V_CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
I/O8
WE
OE
CE
44-pin TSOP 2
NC _{1 44}
NC _{2 43}
A0 3 42
A1 4 41
A2 5 40
A3 6 39
A4 7 38
CE 8 37
I/O1 9 36
I/O2 10 35
V_{CC 11 34}
GND 12 33
I/O3 13 32
I/O4 14 31
WE 15 30
A5 16 29
A6 17 28
A7 18 27
A8 19 26
A9 20 25
NC 21 24
NC 22 23
NC
NC
NC
A18
A17
A16
A15
OE
I/O8
I/O7
GND
V_CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
NC
NC
Selection guide
–10
–12
Maximum address access time
10
12
Maximum outputenable access time
4
5
Maximum operating current
Industrial 180
160
Commercial 170
150
Maximum CMOS standby current
8
8
8/17/04, v. 2.1
Alliance Semiconductor
–15
–20
Unit
15
20
ns
6
7
ns
140
110
mA
130
100
mA
8
8
mA
P. 1 of 9
Copyright © Alliance Semiconductor. All rights reserved.