AS7C34096A-8TIN Datasheet, PDF (1/11 Pages) Alliance Semiconductor Corporation – Fully static operation

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Rev. 1.3
AS7C34096A-8TIN
512K X 8 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev.1.2
Rev.1.3
Description
Initial Issue
.“CE# ≧VCC - 0.2V” revised as ”CE# ≦0.2” for TEST
CONDITION of Average Operating Power supply Current
Icc1 on page3
Add “Green package available” on page 1
1.Revise “TEST CONDITION” for VOH, VOL on page 3
IOH = -8mA revised as -4mA
IOL =4mA revised as 8mA
2. Revise VIH(max) & VIL(min) note on page 3
VIH(max) = VCC + 2.0V for pulse width less than 6ns.
VIL(min) = VSS - 2.0V for pulse width less than 6ns.
Issue Date
July.12. 2012
July.19. 2012
Nov. 02. 2012
June. 04. 2013
Alliance Memory, Inc. reserves the rights to change the specifications and products without notice.
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