AS7C3364NTF32B Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 64K x 32/36 Flowthrough Synchronous SRAM with NTD

April 2005
AS7C3364NTF32B
AS7C3364NTF36B
®
3.3V 64K × 32/36 Flowthrough Synchronous SRAM with NTD^TM
Features
• Organization: 65,536 words × 32 or 36 bits
• NTD^™architecture for efficient bus operation
• Fast clock to data access: 7.5/8.0/10.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
Logic block diagram
16
A[15:0]
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
D
Q
Address
register
Burst logic
CLK
Control
logic
CLK
DQ[a,b,c,d] ^32/36
D ^Data
Input
Q
Register
CLK
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
16
D
Q
Write delay
addr. registers
16
CLK
CLK
32/36
64K x 32/36
SRAM
Array
32/36 32/36
32/36
CLK
CEN
Output
Buffer
OE
32/36
OE
DQ[a,b,c,d]
Selection guide
-75
-80
-10
Units
Minimum cycle time
8.5
10
12
ns
Maximum clock access time
7.5
8.0
10
ns
Maximum operating current
260
230
200
mA
Maximum standby current
110
100
90
mA
Maximum CMOS standby current (DC)
30
30
30
mA
4/28/05, v 1.0
Alliance Semiconductor
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