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AS7C33512PFS18A Datasheet, PDF (1/20 Pages) Alliance Semiconductor Corporation – 3.3V 512K x 18 pipeline burst synchronous SRAM | |||
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November 2004
AS7C33512PFS18A
®
3.3V 512K Ã 18 pipeline burst synchronous SRAM
Features
⢠Organization: 524,288 words à 18 bits
⢠Fast clock speeds to 166 MHz
⢠Fast clock to data access: 3.5/4.0 ns
⢠Fast OE access time: 3.5/4.0 ns
⢠Fully synchronous register-to-register operation
⢠Single-cycle deselect
⢠Asynchronous output enable control
⢠Available in 100-pin TQFP package
⢠Individual byte write and global write
⢠Multiple chip enables for easy expansion
⢠3.3V core power supply
⢠2.5V or 3.3V I/O operation with separate VDDQ
⢠30 mW typical standby power in power down mode
⢠Linear or interleaved burst control
⢠Snooze mode for reduced power-standby
⢠Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[18:0]
GWE
BWb
BWE
BWa
CE0
CE1
CE2
ZZ
OE
19
Power
down
LBO
CLK
CS Burst logic
CLR
19
D
Q
CS
Address
register
CLK
17 19
512K Ã 18
Memory
array
18
18
D DQb Q
Byte Write
registers
CLK
D DQa Q
Byte Write
registers
CLK
D Enable Q
register
CE
CLK
D Enable Q
delay
register
CLK
2
OE
Output
registers
CLK
Input
registers
CLK
18
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
â166
6
166
3.5
475
130
30
11/30/04; v.2.2
Alliance Semiconductor
â133
7.5
133
4
425
100
30
Units
ns
MHz
ns
mA
mA
mA
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