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AS7C33512PFD32A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 512K x 32/36 pipelined burst synchronous SRAM | |||
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February 2005
AS7C33512PFD32A
AS7C33512PFD36A
®
3.3V 512K Ã 32/36 pipelined burst synchronous SRAM
Features
⢠Organization: 524,288 words à 32 or 36 bits
⢠Fast clock speeds to 166 MHz
⢠Fast clock to data access: 3.4/3.8 ns
⢠Fast OE access time: 3.4/3.8 ns
⢠Fully synchronous register-to-register operation
⢠Double-cycle deselect
⢠Asynchronous output enable control
⢠Available in 100-pin TQFP package
⢠Individual byte write and global write
⢠Multiple chip enables for easy expansion
⢠3.3V core power supply
⢠2.5V or 3.3V I/O operation with separate VDDQ
⢠Linear or interleaved burst control
⢠Snooze mode for reduced power-standby
⢠Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[18:0]
GWE
BWE
BWd
BWc
BWb
BWa
CE0
CE1
CE2
ZZ
OE
19
Power
down
LBO
CLK
CE
CLR
Q0
Burst logic
Q1
D
Q 19
17
CE
Address
register
CLK
D DQd Q
Byte write
registers
CLK
D DQc Q
Byte write
registers
CLK
D DQb Q
Byte write
registers
CLK
D DQa Q
Byte write
registers
CLK
D
Q
Enable
CE register
CLK
D Enable Q
delay
register
CLK
512K Ã 32/36
19
Memory
array
36/32
36/32
4
OE
Output
registers
CLK
Input
registers
CLK
36/32
DQ[a:d]
Selection guide
-166
Minimum cycle time
6
Maximum clock frequency
166
Maximum clock access time
3.4
Maximum operating current
300
Maximum standby current
90
Maximum CMOS standby current (DC)
60
-133
7.5
133
3.8
275
80
60
Units
ns
MHz
ns
mA
mA
mA
2/10/05, v 1.3
Alliance Semiconductor
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