AS7C33512NTF18A Datasheet, PDF (1/18 Pages) Alliance Semiconductor Corporation – 3.3V 512K x 18 Flowthrough Synchronous SRAM with NTD

November 2004
AS7C33512NTF18A
®
3.3V 512K×18 Flowthrough Synchronous SRAM with NTD^TM
Features
• Organization: 524,288 words × 18 bits
• NTD^™ architecture for efficient bus operation
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• 30 mW typical standby power
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic Block Diagram
19
A[18:0]
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
FT
LBO
ZZ
D
Q
Address
register
burst logic
CLK
Control
logic
CLK
DQ [a,b]
18
D ^Data
input
Q
register
CLK
CLK
CEN
19
D
Q
Write delay
addr. registers
19
CLK
CLK
512K x 18
SRAM
array
18
18
18
18
Output
buffer
OE
18
OE
DQ [a,b]
Selection Guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-75
-85
-10
8.5
10
12
7.5
8.5
10
280
260
220
120
110
100
30
30
30
Units
ns
ns
mA
mA
mA
11/8/04, v. 1.1
Alliance Semiconductor
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