AS7C33512NTD32A Datasheet, PDF (1/18 Pages) Alliance Semiconductor Corporation – 3.3V 512K x 32/36 Pipelined SRAM with NTD

April 2005
AS7C33512NTD32A
AS7C33512NTD36A
®
3.3V 512K × 32/36 Pipelined SRAM with NTD^TM
Features
• Organization: 524,288 words × 32 or 36 bits
• NTD^™ architecture for efficient bus operation
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.4/3.8 ns
• Fast OE access time: 3.4/3.8 ns
• Fully synchronous operation
• Asynchronous output enable control
• Available in 100-pin TQFP packages
• Individual byte write and global write
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
19
A[18:0]
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
D
Q
Address
register
Burst logic
CLK
Control
logic
CLK
DQ[a,b,c,d] ^32/36
D ^Data
Input
Q
Register
CLK
CLK
CEN
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
19
D
Q
Write delay
addr. registers
19
CLK
CLK
32/36
512K x 32/36
SRAM
Array
32/36 32/36
32/36
CLK
Output
Register
OE
32/36
OE
DQ[a,b,c,d]
-166
-133
6
7.5
166
133
3.4
3.8
300
275
90
80
60
60
Units
ns
MHz
ns
mA
mA
mA
4/21/05, v 2.8
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