AS7C33512NTD18A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 512K x 18 Pipelined burst Synchronous SRAM with NTD

November 2004
AS7C33512NTD18A
®
3.3V 512K × 18 Pipelined burst Synchronous SRAM with NTD^TM
Features
• Organization: 524,288 words × 18 bits
• NTD^™ architecture for efficient bus operation
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/4.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Common data inputs and data outputs
• Asynchronous output enable control
• Available in100-pin TQFP
Logic block diagram
A[18:0]
19
CE0
CE1
CE2
R/W
BWa
BWb
ADV/LD
LBO
ZZ
D _Address ^Q
register
Burst logic
CLK
Control
logic
CLK
18
DQ [a:b]
D ^Data Q
Input
Register
CLK
CLK
CEN
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Self-timed WRITE cycles
• “Interleaved” or “Linear burst” modes
• Snooze mode for standby operation
19
D
Q
Write delay
addr. registers
19
CLK
CLK
512K x 18
SRAM
Array
18
18
18
18
CLK
Output
OE ^Register
18
OE
DQ[a:b]
Selection Guide
-166
Minimum cycle time
6
Maximum clock frequency
166
Maximum clock access time
3.5
Maximum operating current
475
Maximum standby current
130
Maximum CMOS standby current (DC)
30
11/30/04; v.2.1
Alliance Semiconductor
–133
7.5
133
4
400
100
30
Units
ns
MHz
ns
mA
mA
mA
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