AS7C33512FT18A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 512K x 18 Flow-through synchronous SRAM

November 2004
AS7C33512FT18A
®
3.3V 512K × 18 Flow-through synchronous SRAM
Features
• Organization: 524,288 words × 18 bits
• Fast clock to data access: 7.5/8.5/10ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate VDDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[18:0]
GWE
BW_b
BWE
BW_a
CE0
CE1
CE2
ZZ
OE
19
Power
down
LBO
CLK
CS
Burst logic
CLR
D
Q ¹⁹
CS
Address
register
CLK
17 19
512K x 18
Memory
array
18
18
D _DQb Q
Byte Write
registers
CLK
D _DQa Q
Byte Write
registers
CLK
D _Enable Q
register
CE
CLK
D _Enable Q
delay
register
CLK
2
OE
Output
registers
CLK
Input
registers
CLK
18
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-75
-85
-10
Units
8.5
10
12
ns
7.5
8.5
10
ns
300
275
250
mA
110
100
90
mA
30
30
30
mA
11/30/04, v 1.1
Alliance Semiconductor
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