AS7C332MPFD18A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 2M x 18 pipelined burst synchronous SRAM

February 2005
AS7C332MPFD18A
®
3.3V 2M × 18 pipelined burst synchronous SRAM
Features
• Organization: 2,097,152 words × 18 bits
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.1/3.5/3.8 ns
• Fast OE access time: 3.1/3.5/3.8 ns
• Fully synchronous register-to-register operation
• Double-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
21
A[20:0]
GWE
BW_b
BWE
BW_a
CE0
CE1
CE2
ZZ
Power
down
OE
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
LBO
CLK
CS
Burst logic
CLR
21
D
Q
CS
Address
register
CLK
19 21
2M x 18
Memory
array
18
18
D _DQb Q
Byte Write
registers
CLK
D _DQa Q
Byte Write
registers
CLK
D _Enable Q
register
CE
CLK
D _Enable Q
delay
register
CLK
2
OE
Output
registers
CLK
Input
registers
CLK
18
DQ[a,b]
-200
-166
5
6
200
166
3.1
3.5
450
400
170
150
90
90
-133
7.5
133
3.8
350
140
90
Units
ns
MHz
ns
mA
mA
mA
2/10/05, v.1.1
Alliance Semiconductor
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