AS7C332MNTF18A Datasheet, PDF (1/18 Pages) Alliance Semiconductor Corporation – 3.3V 2M x 18 Flowthrough SRAM with NTD

December 2004
AS7C332MNTF18A
®
3.3V 2M x 18 Flowthrough SRAM with NTD^TM
Features
• Organization: 2,097,152 words × 18 bits
• NTD^™architecture for efficient bus operation
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
20
A[19:0]
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
D
Q
Address
register
burst logic
CLK
Control
logic
CLK
DQ [a,b]
18
D ^Data
input
Q
register
CLK
20
D
Q
Write delay
addr. registers
20
CLK
CLK
2M x 18
SRAM
array
18
18
18
18
CLK
CEN
Output
buffer
OE
18
OE
DQ [a,b]
Selection guide
-75
-85
-10
Minimum cycle time
8.5
10
12
Maximum clock access time
7.5
8.5
10
Maximum operating current
325
300
375
Maximum standby current
140
130
130
Maximum CMOS standby current (DC)
90
90
90
Units
ns
ns
mA
mA
mA
12/23/04, v 1.2
Alliance Semiconductor
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