AS7C332MNTD18A Datasheet, PDF (1/18 Pages) Alliance Semiconductor Corporation – 3.3V 2M x 18 Pipelined SRAM with NTD

December 2004
AS7C332MNTD18A
®
3.3V 2M × 18 Pipelined SRAM with NTD^TM
Features
• Organization: 2,097,152 words × 18 bits
• NTD^™ architecture for efficient bus operation
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.2/3.5/3.8 ns
• Fast OE access time: 3.2/3.5/3.8 ns
• Fully synchronous operation
• Common data inputs and data outputs
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
21
A[20:0]
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
D
Q
Address
register
Burst logic
CLK
Control
logic
CLK
DQ[a,b]
18
D ^Data
Input
Q
Register
CLK
21
D
Q
Write delay
addr. registers
21
CLK
CLK
2 M x 18
SRAM
Array
18
18
18
CLK
CEN
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
OE
-200
5
200
3.2
450
170
90
18
CLK
Output
Register
OE
18
DQ[a,b]
-166
-133
6
7.5
166
133
3.5
3.8
400
350
150
140
90
90
Units
ns
MHz
ns
mA
mA
mA
12/23/04, V 1.6
Alliance Semiconductor
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