AS7C33256PFS16A Datasheet, PDF (1/11 Pages) Alliance Semiconductor Corporation – 3.3V 256K × 16/18 pipeline burst synchronous SRAM

March 2001
AS7C33256PFS16A
AS7C33256PFS18A
®
3.3V 256K × 16/18 pipeline burst synchronous SRAM
Features
• Organization: 262,144 words × 16 or 18 bits
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.5/3.8/4.0/5.0 ns
• Fast OE access time: 3.5/3.8/4.0/5.0 ns
• Fully synchronous register-to-register operation
• “Flow-through” mode
• Single-cycle deselect
- Dual-cycle deselect also available (AS7C33256PFD16A/
AS7C33256PFD18A)
• Pentium®^* compatible architecture and timing
• Asynchronous output enable control
• Economical 100-pin TQFP package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• 30 mW typical standby power in power down mode
• NTD™^* pipeline architecture available
(AS7C33256NTD16A/AS7C33256NTD18A)
Logic block diagram
LBO
CLK
ADV
ADSC
ADSP
A[17:0]
CLK
CS _{Burst logic}
256K × 16/18
CLR
Memory
18
D
Q ^{18 16 18}
array
CS ^{Aredgdisrteesrs}
CLK
16/18 ^16/18
GWE
BW_b
BWE
BW_a
CE0
CE1
CE2
ZZ
Power
down
D _DQb Q
Bryetge _iWsterriste
CLK
D _DQa Q
Bryetge _iWsterriste
CLK
D _EnableQ
register
CE
CLK
D _EnableQ
redgeilsatyer
CLK
2
OE
Output
registers
CLK
Input
registers
CLK
OE
DATA [17:0]
FT _{DATA [15:0]}
Pin arrangement
NC 1
NC 2
NC 3
V_DDQ 4
V_SSQ 5
NC 6
NC 7
DQb 8
DQb 9
V_SSQ 10
V_DDQ 11
DQb 12
DQb 13
FT 14
V_DD 15
NC 16
V_SS 17
DQb 18
DQb 19
V_DDQ 20
V_SSQ 21
DQb 22
DQb 23
DQpb/NC 24
NC 25
V_SSQ 26
V_DDQ 27
NC 28
NC 29
NC 30
TQFP 14 × 20mm
80 A17
79 NC
78 NC
77 VDDQ
76 VSSQ
75 NC
74 DQpa/NC
73 DQa
72 DQa
71 VSSQ
70 VDDQ
69 DQa
68 DQa
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 NC
56 NC
55 VSSQ
54 VDDQ
53 NC
52 NC
51 NC
Note: pins 24, 74 are NC for ×16.
Selection guide
AS7C33256PFS16A AS7C33256PFS16A AS7C33256PFS16A AS7C33256PFS16A
–166
–150
–133
–100
Units
Minimum cycle time
6
6.7
7.5
10
ns
Maximum pipelined clock frequency
166
150
133
100
MHz
Maximum pipelined clock access time
3.5
3.8
4
5
ns
Maximum operating current
475
450
425
325
mA
Maximum standby current
130
110
100
90
mA
Maximum CMOS standby current (DC)
30
30
30
30
mA
*_Pentium® _{is a registered trademark of Intel Corporation. NTD™ is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are}
the property of their respective owners.
3/14/01; V.1.0
Alliance Semiconductor
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