AS7C33256NTF32A Datasheet, PDF (1/18 Pages) Alliance Semiconductor Corporation – 3.3V 256K x 2/36 Flowthrough Synchronous SRAM with NTD

November 2004
AS7C33256NTF32A
AS7C33256NTF36A
®
3.3V 256K×32/36 Flowthrough Synchronous SRAM with NTD^TM
Features
• Organization: 262,144 words × 32 or 36 bits
• NTD^™ architecture for efficient bus operation
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
Logic Block Diagram
A[17:0]
18
D
Q
Address
register
Burst logic
CLK
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
Control
logic
CLK
DQ[a,b,c,d] ^32/36
D ^Data
Input
Q
Register
CLK
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• 30 mW typical standby power
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
18
D
Q
Write delay
addr. registers
18
CLK
CLK
32/36
256K x 32/36
SRAM
Array
32/36 32/36
CLK
CEN
Selection Guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
32/36
Output
Buffer
OE
32/36
OE
DQ[a,b,c,d]
-75
-85
-10
Units
8.5
10
12
ns
7.5
8.5
10
ns
300
280
240
mA
120
110
100
mA
30
30
30
mA
11/8/04, v. 1.1
Alliance Semiconductor
P. 1 of 18
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