AS7C33256NTD32A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 256K x 2/36 Pipelined burst Synchronous SRAM with NTD

November 2004
AS7C33256NTD32A
AS7C33256NTD36A
®
3.3V 256K×32/36 Pipelined burst Synchronous SRAM with NTD^TM
Features
• Organization: 262,144 words × 32 or 36 bits
• NTD^™architecture for efficient bus operation
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.5/4.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Common data inputs and data outputs
• Asynchronous output enable control
• Available in 100-pin TQFP
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic Block Diagram
A[17:0]
18
CE0
CE1
CE2
R/W
BWa
BWb
BWc
BWd
ADV / LD
LBO
ZZ
DQ [a:d] ^36/32
D _AddressQ
register
Burst logic
CLK
Control
logic
CLK
D
Data
Input
Q
Register
CLK
18
D
Q
Write delay
addr. registers
18
CLK
CLK
36/32
256K x 32/36
SRAM
Array
36/32 36/32
CLK
CEN
Selection Guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
36/32
CLK
Output
Register
OE
36/32
OE
DQ[a:d]
-166
-133
6
7.5
166
133
3.5
4
475
400
130
100
30
30
Units
ns
MHz
ns
mA
mA
mA
11/30/04, v. 2.1
Alliance Semiconductor
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