AS7C33256FT18B Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 256K x 18 Flow Through Synchronous SRAM

December 2004
AS7C33256FT18B
®
3.3V 256K × 18 Flow Through Synchronous SRAM
Features
• Organization: 262,144 words × 18 bits
• Fast clock to data access: 6.5/7.5/8.0/10.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow through operation
• Asynchronous output enable control
• Availalbe in 100-pin TQFP package
• Individual byte write and Global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Linear or interleaved burst control
• Snooze mode for reduced power standby
• Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[17:0]
GWE
BW_b
BWE
BW_a
CE0
CE1
CE2
ZZ
OE
18
Power
down
LBO
CLK
CS _{Burst logic}
CLR
D
Q
2
2
CS
Address
register
18
16 18
CLK
256K × 18
Memory
array
D _DQb Q
Byte Write
registers
CLK
D _DQa Q
Byte Write
registers
CLK
D _Enable Q
register
CE
CLK
D _Enable Q
delay
register
CLK
18 18
2
OE
Output
Buffers
Input
registers
CLK
18
DQ [a,b]
Selection guide
–65
-75
-80
-10
Units
Minimum cycle time
7.5
8.5
10
12
ns
Maximum clock access time
6.5
7.5
8.0
10.0
ns
Maximum operating current
250
225
200
175
mA
Maximum standby current
120
100
90
90
mA
Maximum CMOS standby current (DC)
30
30
30
30
mA
12/10/04; v.1.4
Alliance Semiconductor
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