|
AS7C331MPFS18A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 1M x 18 pipelined burst synchronous SRAM | |||
|
December 2004
AS7C331MPFS18A
®
3.3V 1M x 18 pipelined burst synchronous SRAM
Features
⢠Organization: 1,048,576 x18 bits
⢠Fast clock speeds to 166MHz
⢠Fast clock to data access: 3.4/3.8 ns
⢠Fast OE access time: 3.4/3.8 ns
⢠Fully synchronous register-to-register operation
⢠Single-cycle deselect
⢠Asynchronous output enable control
⢠Available 100-pin TQFP package
⢠Individual byte write and global write
⢠Multiple chip enables for easy expansion
⢠3.3 V core power supply
⢠2.5 V or 3.3V I/O operation with separate VDDQ
⢠Linear or interleaved burst control
⢠Common data inputs and data outputs
⢠Snooze mode for reduced power-standby
Logic block diagram
CLK
ADV
ADSC
ADSP
A[19:0]
GWE
BWb
BWE
BWa
CE0
CE1
CE2
ZZ
OE
20
Power
down
LBO
CLK
CS Burst logic
CLR
D
Q 20
CS
Address
register
CLK
18 20
1M x 18
Memory
array
18
18
D DQb Q
Byte Write
registers
CLK
D DQa Q
Byte Write
registers
CLK
D Enable Q
register
CE
CLK
D Enable Q
delay
register
CLK
2
OE
Output
registers
CLK
Input
registers
CLK
18
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-166
-133
6
7.5
166
133
3.4
3.8
290
270
90
80
60
60
Units
ns
MHz
ns
mA
mA
mA
12/23/04, v 2.6
Alliance Semiconductor
1 of 19
Copyright © Alliance Semiconductor. All rights reserved.
|
▷ |