AS7C331MNTD18A Datasheet, PDF (1/18 Pages) Alliance Semiconductor Corporation – 3.3V 1M x 18 Pipelined SRAM with NTD

December 2004
AS7C331MNTD18A
®
3.3V 1M x 18 Pipelined SRAM with NTD^TM
Features
• Organization: 1,048,576 words × 18 bits
• NTD^™ architecture for efficient bus operation
• Fast clock speeds to 166 MHz
• Fast clock to data access: 3.4/3.8 ns
• Fast OE access time: 3.4/3.8 ns
• Fully synchronous operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
20
A[19:0]
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
D
Q
Address
register
burst logic
CLK
Control
logic
CLK
DQ [a,b]
18
D ^Data
input
Q
register
CLK
CLK
CEN
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
20
D
Q
Write delay
addr. registers
20
CLK
CLK
1M x 18
SRAM
array
18
18
18
18
CLK
Output
register
OE
18
OE
DQ [a,b]
-166
-133
6
7.5
166
133
3.4
3.8
290
270
90
80
60
60
Units
ns
MHz
ns
mA
mA
mA
12/24/04, v 2.7
Alliance Semiconductor
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