AS7C331MFT32A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 1M x 32/36 Flow-through synchronous SRAM

December 2004
AS7C331MFT32A
AS7C331MFT36A
®
3.3V 1M × 32/36 Flow-through synchronous SRAM
Features
• Organization: 1,048,576 words × 32 or 36 bits
• Fast clock to data access: 7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[19:0]
GWE
BWE
BW_d
BW_c
BW_b
BW_a
CE0
CE1
CE2
ZZ
OE
20
Power
down
LBO
CLK
CE
CLR
Q0
Burst logic
Q1
D
Q
2
CE
Address
register
20 18
CLK
D _DQd Q
Byte write
registers
CLK
D _DQc Q
Byte write
registers
CLK
D _DQb Q
Byte write
registers
CLK
D _DQa Q
Byte write
registers
CLK
D
Q
Enable
CE register
CLK
D _Enable Q
delay
register
CLK
1M × 32/36
Memory
2
array
20
32/36
32/36
4
OE
Output
registers
CLK
Input
registers
CLK
32/36
DQ[a:d]
Selection guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-75
-85
-10
8.5
10
12
7.5
8.5
10
325
300
275
140
130
130
90
90
90
Units
ns
ns
mA
mA
mA
12/23/04, v 1.3
Alliance Semiconductor
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