AS7C331FT18A Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 1M x 18 Flow-through synchronous SRAM

January 2005
AS7C331MFT18A
®
3.3V 1M x 18 Flow-through synchronous SRAM
Features
• Organization: 1,048,576 words x18 bits
• Fast clock to data access: 6.8/7.5/8.5/10 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous flow-through operation
• Asynchronous output enable control
• Available 100-pin TQFP packages
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3 V core power supply
• 2.5 V or 3.3V I/O operation with separate V_DDQ
• Linear or interleaved burst control
• Common data inputs and data outputs
• Snooze mode for reduced power-standby
Logic block diagram
CLK
ADV
ADSC
ADSP
A[19:0]
GWE
BW_b
BWE
BW_a
CE0
CE1
CE2
ZZ
OE
20
Power
down
LBO
CLK
CS _{Burst logic}
CLR
D
Q ²⁰
CS
Address
register
CLK
18 20
1M x 18
Memory
array
18
18
D _DQb Q
Byte Write
registers
CLK
D _DQa Q
Byte Write
registers
CLK
D _Enable Q
register
CE
CLK
D _Enable Q
delay
register
CLK
2
OE
Output
buffers
Input
registers
CLK
18
DQ[a,b]
Selection guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-68
-75
-85
7.5
8.5
10
6.8
7.5
8.5
285
275
250
90
90
80
60
60
60
-10
Units
12
ns
10
ns
230
mA
80
mA
60
mA
1/21/05, v 1.4
Alliance Semiconductor
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