AS7C33128PFS32A Datasheet, PDF (1/13 Pages) Alliance Semiconductor Corporation – 3.3V 128K X 32/36 pipeline burst synchronous SRAM

March 2002
AS7C33128PFS32A
AS7C33128PFS36A
®
3.3V 128K X 32/36 pipeline burst synchronous SRAM
Features
• Organization: 131,072 words × 32 or 36 bits
• Fast clock speeds to 200 MHz in LVTTL/LVCMOS
• Fast clock to data access: 3.0/3.1/3.5/4.0/5.0 ns
• Fast OE access time: 3.0/3.1/3.5/4.0/5.0 ns
• Fully synchronous register-to-register operation
• Single register “Flow-through” mode
• Single-cycle deselect
• Dual-cycle deselect also available (AS7C33128PFD32A/
AS7C33128PFD36A)
• Pentium®¹ compatible architecture and timing
• Asynchronous output enable control
• Economical 100-pin TQFP package
• Byte write enables
• Multiple chip enables for easy expansion
• 3.3 core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• 30 mW typical standby power in power down mode
• NTD™¹ pipeline architecture available
(AS7C33128NTD32A/ AS7C33128NTD36A)
1 Pentium^® is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks
mentioned in this document are the property of their respective owners.
Logic block diagram
Pin arrangement
CLK
ADV
ADSC
ADSP
A[16:0]
GWE
BWE
BW_d
BW_c
BW_b
BW_a
CE0
CE1
CE2
ZZ
OE
LBO
CLK
CE
Q0
Burst logic
CLR
17
D
Q1
128K × 32/36
Q ¹⁷
15
17
Memory
array
CE
Address
register
CLK
D _DQd Q
Byte write
registers
CLK
D _DQc Q
Byte write
registers
CLK
D _DQb Q
Byte write
registers
CLK
D _DQa Q
Byte write
registers
CLK
36/32
36/32
4
Power
down
D
Q
Enable
CE register
CLK
D _Enable Q
delay
register
CLK
OE
Output
registers
CLK
Input
registers
CLK
36/32
FT _{DQ [a:d]}
DQP_c/NC 1
DQ_c 2
DQ_c 3
V_DDQ 4
V_SSQ 5
DQ_c 6
DQ_c 7
DQ_c 8
DQ_c 9
V_SSQ 10
V_DDQ 11
DQ_c 12
DQ_c 13
FT 14
V_DD 15
NC 16
V_SS 17
DQ_d 18
DQ_d 19
V_DDQ 20
V_SSQ 21
DQ_d 22
DQ_d 23
DQ_d 24
DQ_d 25
V_SSQ 26
V_DDQ 27
DQ_d 28
DQ_d 29
DQP_d/NC 30
TQFP 14 × 20 mm
80 DQP_b/NC
79 DQ_b
78 DQ_b
77 VDDQ
76 VSSQ
75 DQ_b
74 DQ_b
73 DQ_b
72 DQ_b
71 VSSQ
70 VDDQ
69 DQ_b
68 DQ_b
67 V_SS
66 NC
65 VDD
64 ZZ
63 DQ_a
62 DQ_a
61 VDDQ
60 VSSQ
59 DQ_a
58 DQ_a
57 DQ_a
56 DQ_a
55 VSSQ
54 VDDQ
53 DQ_a
52 DQ_a
51 DQP_a/NC
Note: Pins 1,30,51,80 are NC for ×32
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum pipelined clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
–200
5
200
3
570
160
30
–183
5.4
183
3.1
540
140
30
–166
6
166
3.5
475
130
30
–133
7.5
133
4
425
100
30
–100
10
100
5
325
90
30
Units
ns
MHz
ns
mA
mA
mA
3/4/02; v.1.4
Alliance Semiconductor
P. 1 of 13
Copyright © Alliance Semiconductor. All rights reserved.