AS7C33128PFS18B Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 128K x 18 pipeline burst synchronous SRAM

December 2004
AS7C33128PFS18B
®
3.3V 128K × 18 pipeline burst synchronous SRAM
Features
• Organization: 131,072 words × 18 bits
• Fast clock speeds to 200 MHz
• Fast clock to data access: 3.0/3.5/4.0 ns
• Fast OE access time: 3.0/3.5/4.0 ns
• Fully synchronous register-to-register operation
• Single-cycle deselect
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Individual byte write and global write
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Linear or interleaved burst control
• Snooze mode for reduced power-standby
• Common data inputs and data outputs
Logic block diagram
CLK
ADV
ADSC
ADSP
A[16:0]
GWE
BW_b
BWE
BW_a
CE0
CE1
CE2
ZZ
OE
17
Power
down
LBO
CLK
CS _{Burst logic}
CLR
D
Q
CS
Address
register
17
CLK
15 17
128K × 18
Memory
array
D _DQb Q
Byte Write
registers
CLK
D _DQa Q
Byte Write
registers
CLK
D _Enable Q
register
CE
CLK
D _Enable Q
delay
register
CLK
18 18
2
OE
Output
registers
CLK
Input
registers
CLK
18
DQ [a,b]
Selection guide
Minimum cycle time
Maximum clock frequency
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
–200
5
200
3.0
375
130
30
–166
6
166
3.5
350
100
30
–133
7.5
133
4
325
90
30
Units
ns
MHz
ns
mA
mA
mA
12/10/04; v.1.4
Alliance Semiconductor
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