AS7C33128NTF18B Datasheet, PDF (1/19 Pages) Alliance Semiconductor Corporation – 3.3V 128K x 18 Flowthrough Synchronous SRAM with NTD

April 2005
AS7C33128NTF18B
®
3.3V 128K x 18 Flowthrough Synchronous SRAM with NTD^TM
Features
• Organization: 131,072 words × 18 bits
• NTD^™ architecture for efficient bus operation
• Fast clock to data access: 7.5/8.0/10.0 ns
• Fast OE access time: 3.5/4.0 ns
• Fully synchronous operation
• Flow-through mode
• Asynchronous output enable control
• Available in 100-pin TQFP package
• Byte write enables
• Clock enable for operation hold
• Multiple chip enables for easy expansion
• 3.3V core power supply
• 2.5V or 3.3V I/O operation with separate V_DDQ
• Self-timed write cycles
• Interleaved or linear burst modes
• Snooze mode for standby operation
Logic block diagram
17
A[16:0]
CE0
CE1
CE2
R/W
BWa
BWb
ADV / LD
LBO
ZZ
D
Q
Address
register
burst logic
CLK
Control
logic
CLK
DQ [a,b]
18
D ^Data
input
Q
register
CLK
CLK
CEN
17
D
Q
Write delay
addr. registers
17
CLK
CLK
128K x 18
SRAM
array
18
18
18
18
Output
buffer
OE
18
OE
DQ [a,b]
Selection guide
Minimum cycle time
Maximum clock access time
Maximum operating current
Maximum standby current
Maximum CMOS standby current (DC)
-75
-80
-10
8.5
10
12
7.5
8.0
10
260
230
200
110
100
90
30
30
30
Units
ns
ns
mA
mA
mA
4/28/05, v 1.0
Alliance Semiconductor
P. 1 of 19
Copyright © Alliance Semiconductor. All rights reserved.